Services - FPGA / CPLD Design
DesignLinx engineers are FPGA experts who become a trusted extension of your engineering team. From small CPLDs to complex SoC FPGAs, we deliver reliable designs that speed development time and free up internal resources, allowing you to focus on other mission critical tasks. DesignLinx can offer you:
  • Turn-key designs
    • We will work with you and based on that collaboration we will develop the design specification and then implement that design in the FPGA(s) of your choice.
  • Design to your specification
    • We design the FPGA(s) to your specification and meet your needed constraints.
  • Upgrade legacy designs
    • We can help you port designs to newer components due to possible obsolescence issues or cost reduction redesigns.
  • Expertise
    • Verilog, VHDL
    • Tool & Device Support for Altera, Lattice, Tabula and Xilinx
    • HDL optimization techniques
    • Assistance with complex clocking schemes
    • Memory Interfaces – DDR2, DDR3, LPDDR, NAND, NOR
    • DSP, Gigabit Transceivers, PCIe , Gigabit Ethernet
    • Simulation/Verification/Lab Debug
    • FPGA timing closure / design for performance
      • Resource utilization
      • High fan-out, multiple levels of logic partitioning
      • Optimization of synthesis results
      • Design tools and advanced implementation techniques, indentifying problematic elements of HDL
    • Embedded Processing
      • Experience with Nios, MicroBlaze, ARM and PPC including Avalon, AXI and PLB
      • Multi-core experience ranging from tightly coupled processors to completely independent processors
      • Expertise in partitioning between hardware and software for maximum performance
    • MGT / High Speed Serial IO (SERDES)
      • Optimize implementation of high speed serial channels utilizing SERDES cores
      • Power, clocking, PCB routing and signal integrity
      • Architecture and protocol requirements tradeoffs
      • Test plan development
      • ChipScope Serial I/O Toolkit for SERDES configuration and BER optimization
      • Schematics and PCB review to meet guidelines and requirements
      • Experienced in designs from <100Mbs to >10Gbs
      • IP Cores
        • PCIe, XAUI, Serial Rapid IO, etc...
        • Design requirements for configuration
To submit a proposal for a new engagement, please click here.