To provide our customers with state-of-the-art compute power for dense FPGA designs, the DesignLinx ITAR EnclaveTM contains high-end compute servers, along with a secure file transfer service that features enhanced encryption and two-factor authentication. When we receive your ITAR-controlled data, the DesignLinx ITAR Enclave becomes your vault. Our ITAR Enclave is US-based, housed separately, and access is restricted to US citizens only. It is locked and monitored under motion-sensed video surveillance.
The International Traffic In Arms Regulations (ITAR) controls the export and import of defense-related articles and services on the United States Munitions List (USML). According to the US State Department, not only do manufacturers, exporters, and brokers of defense articles need to be compliant, but providers of defense services—and all related technical data—must be ITAR compliant as well. DesignLinx is registered with the Directorate of Defense Trade Controls (DDTC) at the US Department of State, and is compliant with ITAR guidelines.
UltraFast Design Methodology
ASIC-Level Verification/Simulation
UVM Verification
DSP Algorithm Implementation
Schematic Layout
Schematic Integrity
Signal Integrity
High-layer count boards (36+)
Micro-vias, blind and buried vias
Flex and Rigid Flex
Fine pitch (<0.5mm) BGA technology
Metal-Core PCB
Controlled impedances, differential pairs, matched trace lengths
Design for manufacturing
Verilog
System Verilog
UVM
VHDL
C/C++
Python
Drivers Development
Bootstrapping
Bare metal
Linux configuration and build
Device tree programming
AMP/SMP techniques and implementation
MicroBlaze multiprocessing
Flash file system creation, partitioning, and more
Simulation with QEMU
Linux
FreeRTOS
vxWorks
RFSoC
Zynq UltraScale+
Zynq 7000
MicroBlaze
Vivado
ISE
SDAccel
SDSoC
HLS
ModelSim
Questa (Questa ReqTracer)
Matlab
“DesignLinx has provided us with operational solutions for an Asynchronous Multi-Processor deployment on the Zynq architecture. This solution included inter-processor communications and a move to a more sustainable build process using Buildroot. Our system can now properly operate with FreeRTOS on CPU1 and a Linux distro on CPU0. DesignLinx has been instrumental in getting this up and running, and continues to provide support as we better understand the Xilinx caching approach in the different versions of their releases.”
